1. Field of the Invention
Embodiments of the invention generally relate to electronic design automation and, more specifically, to a method and apparatus for translating a verification process having recursion for implementation in a logic emulator.
2. Description of the Related Art
In electronic design automation (EDA), functional verification is the task of verifying that a logic design conforms to its specification before the logic design is manufactured as integrated circuits (ICs). Logic designs may be described using various languages, such as hardware description languages (HDLs) or other more abstract languages (e.g., synthesizable SystemC). Functional verification can be performed using a hardware emulation system, where the logic design is mapped into an emulator to provide a design under verification (DUV). As used herein, an “emulator” refers to any type of hardware in which the design runs, such as emulator, hardware accelerator, or the like. Such emulation systems allow a design to run much faster than pure software simulation on a general-purpose computer or workstation.
In logic verification, engineers create a test design to functionally verify the logic design by providing verification processes to check that, given certain input stimuli, the design performs to specification. A test design may be written using various languages, including lower-level languages, such as very high speed integrated circuit HDL (VHDL), Verilog, and the like, as well as more abstract languages, such as C/C++, SystemC, SystemVerilog, and the like. Notably, some verification processes can be defined efficiently using recursive tasks (e.g., a task that repeatedly calls itself until some condition is satisfied). In some cases, there is no direct method to define a verification process without using one or more recursive tasks.
Hardware emulators typically include programmable logic devices or other types of integrated circuits (ICs) in which the DUV is implemented. As such, all design and verification processes must be transformed into gate-level logic before such processes can run on the hardware. For example, such processes can be synthesized and a physical hardware implementation formed for a target emulator. However, in most hardware description languages, recursive tasks are not synthesizable and cannot be directly mapped to gate-level logic of a hardware implementation for emulation. As such, verification processes that utilize recursive tasks must be implemented in software and executed on a general-purpose computer system or workstation. Such software verification processes must use co-simulation interfaces to work with the emulator. Software simulation is inherently slower than the hardware simulation, and thus the recursive tasks run slower and less efficiently as compared to the design under verification. As a result, the logic verification process is slower and less efficient as compared to pure hardware systems.
Accordingly, there exists a need in the art for a method and apparatus for translating recursive logic verification processes of a logic design into synthesizable constructs for mapping onto gate-level logic.